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| TECHNICAL DATA IW4503B Hex Buffer High-Voltage Silicon-Gate CMOS The IW4503B is a hex noninverting buffer with 3-state outputs having high sink- and source-current capability. Two output ENABLE controls are provided, one of which controls four buffers and the other controls the remaining two buffers. * Operating Voltage Range: 3.0 to 18 V * Maximum input current of 1 A at 18 V over full package-temperature range; 100 nA at 18 V and 25C * Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply ORDERING INFORMATION IW4503BN Plastic IW4503BD SOIC TA = -55 to 125 C for all packages LOGIC DIAGRAM PIN ASSIGNMENT FUNCTION TABLE Inputs Enable 1,Enable 2 L L H Z = high impedance X = don't care PIN 16=VCC PIN 8= GND A L H X Output Y L H Z Rev. 00 IW4503B MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN PD PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Power Dissipation per Output Transistor Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +20 -0.5 to VCC +0.5 -0.5 to VCC +0.5 10 750 500 100 -65 to +150 260 Unit V V V mA mW mW C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Min 3.0 0 -55 Max 18 VCC +125 Unit V V C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. Rev. 00 IW4503B DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol VIH Parameter Minimum High-Level Input Voltage Maximum Low Level Input Voltage Minimum High-Level Output Voltage Maximum Low-Level Output Voltage Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Minimum Output Low (Sink) Current Test Conditions VOUT= VCC - 0.5V VOUT= VCC - 1.0 V VOUT= VCC - 1.5V VOUT=0.5 V VOUT=1 V VOUT=1.5 VIN= VCC V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 18 5.0 10 15 20 5.0 10 15 5.0 5.0 10 15 18 Guaranteed Limit -55C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 0.1 1 2 4 20 2.6 6.5 19.2 -1.2 -5.8 -3.1 -8.2 0.4 25C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 0.1 1 2 4 20 2.1 5.5 16.1 -1.02 -4.8 -2.6 -6.8 0.4 125 C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 1.0 30 60 120 600 1.3 3.8 11.2 mA -0.7 -3 --1.8 -4.8 12 A Unit V VIL V VOH V VOL VIN=GND V IIN ICC VIN= GND or VCC VIN= GND or VCC A A IOL VIN= GND or VCC UOL=0.4 V UOL=0.5 V UOL=1.5 V mA IOH Minimum Output VIN= GND or VCC High (Source) Current UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V Maximum Tree-State Leakage Current Output in High-Impedance State VIN= GND or VCC VOUT= GND or VCC IOZ Rev. 00 IW4503B AC ELECTRICAL CHARACTERISTICS (CL=50pF, RL=200k unless otherwise specified, Input tr=tf=20 ns) VCC Symbol tPLH Parameter Maximum Propagation Delay, Input A to Output Y (Figure 1) Maximum Propagation Delay, Input A to Output Y (Figure 1) Maximum Propagation Delay, Output Enable to Output Y (Figure 2) RL = 1 k Maximum Propagation Delay, Output Enable to Output Y (Figure 2) RL = 1 k Maximum Output Transition Time, Any Output (Figure 1) Maximum Output Transition Time, Any Output (Figure 1) Maximum Input Capacitance Maximum Tree-State Output Capacitance (Output in High-Impedance State) V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 150 70 50 110 50 35 140 60 50 180 80 70 90 45 35 70 40 25 Guaranteed Limit -55C 25C 150 70 50 110 50 35 140 60 50 180 80 70 90 45 35 70 40 25 7.5 15 125C 300 140 100 220 100 70 280 120 100 360 160 140 180 90 70 140 80 50 Unit ns tPHL ns tPHZ, tPZH ns tPZL, tPLZ ns tTLH ns tTHL ns CIN COUT pF pF Figure 1. Switching Waveforms Figure 2. Switching Waveforms Rev. 00 IW4503B EXPANDED LOGIC DIAGRAM (1/6 of the Device) Rev. 00 IW4503B N SUFFIX PLASTIC DIP (MS - 001BB) A Dimension, mm 16 9 B Symbol A MIN 18.67 6.1 MAX 19.69 7.11 5.33 1 8 B C F L D F 0.36 1.14 2.54 7.62 0 2.92 7.62 0.2 0.38 0.56 1.78 C -T- SEATING PLANE G H H J N G D 0.25 (0.010) M T K M J K L M N 10 3.81 8.26 0.36 NOTES: 1. Dimensions "A", "B" do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side. D SUFFIX SOIC (MS - 012AC) Dimension, mm A 16 9 Symbol A MIN 9.8 3.8 1.35 0.33 0.4 1.27 5.72 0 0.1 0.19 5.8 0.25 MAX 10 4 1.75 0.51 1.27 H B P B C 1 G 8 C R x 45 D F G -TD 0.25 (0.010) M T C M K SEATING PLANE J F M H J K M P R 8 0.25 0.25 6.2 0.5 NOTES: 1. Dimensions A and B do not include mold flash or protrusion. 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B 0.25 mm (0.010) per side. Rev. 00 |
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